Responsible for this page: Mark Vesterbacka , markv@isy.liu.se
Page last update: 2008-05-08
Responsible for this page: Mark Vesterbacka , markv@isy.liu.se
Page last update: 2008-05-08
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The project Algorithms and circuit techniques for increased performance of data converters started 1 Jan. 2001, and ended 31 Dec. 2002. It is continued since 1 Jan. 2003 with the project Reduction of substrate noise in mixed-signal circuits.
The data converter is one of the bottlenecks in wideband telecommunication applications where high speed and high accuracy are required. The design of the analog front-end is also becoming more difficult as we are heading towards single-chip solutions. There will also be more digital signal processing circuits within the data converters in the future. Major issues in single-chip systems are the use of a common substrate for the digital and analog circuits, and the use of low-cost digital CMOS processes. This project aims at alleviating the problems incurred in the analog domain by using digital circuit techniques and algorithms.
We have started our work by addressing a subproblem associated with the common substrate of the digital and analog circuits. There is an incompatibility between the two circuit types in that digital circuits generate more noise than analog circuits, but they are on the other hand more insensitive to disturbances. Hence, sharing of the substrate causes the digital circuit noise to be propagated in the substrate to the sensitive analog circuits, degrading their performance. The design of such a system will be increasingly more difficult as the digital part becomes larger.
Our approach to solve this problem is to reduce the amount of noise generated by the digital circuits. We have developed a strategy that aims at reducing the digital circuit noise originating in the clock distribution network. The basic idea is to reduce the high frequency content of the clock noise by using smooth clock edges and a special digital register. The remaining low frequency noise is then reduced with conventional design techniques. This approach should also reduce the noise in a well-designed power distribution network, since smaller, less noisy, drivers are utilized. The strategy is currently being evaluated in a test chip. We believe that the outcome of the work will be beneficial in improving the performance of data converters as well as other analog and mixed-signal circuits in large system designs.
Our topic of interest concerns the integration of analog and mixed-signal circuits in a CMOS silicon chip. The substrate for the devices in an integrated circuit commonly consists of doped silicon that has a rather high resistivity. However, the resistivity is not so high that the coupling between the different parts of the chip can be neglected. Noise produced in a circuit can easily propagate through the substrate to other circuits. There are two main types of substrate; lightly and heavily doped substrate. A heavily doped substrate actually consists of two different layers. The thin top layer (epitaxial) consists of lightly doped silicon of a few µm and a thicker layer beneath of heavily doped silicon of a few hundreds µm. The heavily doped layer has relatively low resistivity and can with good approximation be treated as a single node. The noise is approximately independent of the distance between the circuits as soon as the distance is a few times larger than the thickness of the thin layer. With the heavily doped layer beneath the risk of latch-up is reduced dramatically, which makes it a good substrate for digital circuits. A lightly doped substrate does on the other hand consist of a single layer of lightly doped silicon with high resistivity. Experimental results show that the noise coupling is approximately reduced as r^-1.5 where r is the distance between the noise source and the receiving circuit. Hence, this type of substrate is preferred for mixed-signal circuits since the noise can be reduced by increasing the distance between the circuits.
Most of the noise in a mixed-signal chip is generated when the digital circuits switch. This noise is injected via the capacitive coupling of the switching nodes into the substrate. Another source of noise is voltage fluctuations on the power supply lines that are triggered by the switching. These fluctuations occur due to a resonant circuit formed by the capacitance of the circuits and the inductance of the bonding wires that are used to connect the chip with the package pins (illustrated in Fig. 1). This kind of noise is referred to as simultaneous switching noise and it manifests as an oscillation in the power supply lines. To reduce the fluctuations, many parallel connections are used to power the circuits, hence the inductance is reduced, and the resonance in the power supply needs to be designed. Separate power supply lines to the analog and digital circuits are used to protect the analog circuits, but since there commonly are substrate contacts biased by the power supply, the simultaneous switching noise is still propagated to the analog circuits via the substrate.
On its path to the sensitive analog circuits, the noise is dampened by the resistance of the substrate and by other measures the integrated circuit designer has taken in order to reduce the noise. Examples on such measures are so called guard rings that connect substrate areas surrounding the circuits to the power supply via a low-impedance path, and active circuits that cancel the noise. Common for the methods is that the low frequency noise can be reduced well, while they have little effect on the high frequency noise. The noise is received by the devices in the analog circuits due to the corresponding capacitive coupling to the circuit node. The noise is also affecting the voltage beneath the MOSFET channels, which takes part in controlling the device currents, adding further noise to the analog signals. The noise injection and rejection path from the noisy digital circuits to the sensitive analog circuits is depicted in Fig. 2.
Figure 1: Off-chip to on-chip connection.
Figure 2: Noise injection and reception in a shared substrate.
In this work we have studied the noise transfer mechanisms in mixed analog and digital single-chip systems. The objective is to reduce the noise emitted from the digital circuits as well as the noise received by the analog circuits. A model of the noise transfer has been developed by the use of the finite element method. With the tool FEMLAB, a mesh of the substrate could be generated, which was reduced to a three-node circuit. The full model was obtained by including the parasitic inductances of the interconnect from chip to off-chip. A significant noise source in a single-chip system is the digital clock network where large current peaks are present in the clock and power supply nodes due to a very large load. Since it is particularly difficult to dampen the high frequency components of the noise, we have developed a strategy of reducing the high frequency content of the clock signal. In the approach, a clock with smooth edges is used, i.e., the high frequency components are reduced, and a special digital register that can operate with long rise and fall times of the clock [1].
A model of the noise transfer in a mixed-signal chip has been developed which is valid up to a frequency of a few GHz. The simulation of the model yields that a high frequency component is significantly less attenuated in the substrate compared to a low frequency component [2, 3].
A test chip has been designed and implemented [2, 3] according to the proposed noise reduction strategy above. The design allows control of the rise and fall time of the clock in a digital lowpass filter designed for VDSL applications [4], different guard ring configurations can be evaluated, and the performance of two analog lowpass filters is measured. The structure of the test chip is shown in Fig. 3. The digital filter is a 13th-order FIR filter implemented with bit-parallel carry-save arithmetic using DCVS logic and the special register. There is also a special clock buffer for which the rise and fall times can be programmed individually in 255 steps. The analog filters are two fifth-order leapfrog filters implemented in active-RC technique, placed at different locations relative to the digital circuit. There are also three different guard rings implemented that can be activated individually to evaluate the effect of different guard ring design. The test chip was manufactured in AMS 0.35 µm CMOS process with two poly layers and three metal layers. A photograph of the chip is shown in Fig. 4. The clock generator and the digital filter is visible to the left and the two active filters consisting of an array of operational amplifiers and an array of unit capacitors each can be seen to the right. The core area of the circuit is 3.6 mm * 2.0 mm and the die area is 4.3 mm * 2.6 mm.
Figure 3: Structure of the test chip.
Figure 4: Chip photograph.
So far the functionality of the chip has been verified. Some preliminary results are shown in Table 1. Notably the maximal sample frequency and the power consumption remain approximately constant with decreasing sharpness of the clock edges, which is good. From simulations they were expected to drop and increase slightly, respectively. Further measurements will be conducted to verify these results as well as measuring of the analog filter performance. The measurement environment is shown in Fig. 5. In the photograph we can see dr. student Erik Backenius manipulating the test board. The used instrumentation consists of an HP 16500C pattern generator and logic analyzer, a HP 66312A DC source, and a FLUKE 45 multimeter, along with some Al-foil used for shielding.
Figure 5: Measurement environment.
The digital part of the chip is currently being characterized over the intended parameter range; i.e. different inputs, rise and fall time of the clock, varying clock frequency and power supply voltage. After this we will measure the noise and the tones at multiples of the clock frequency of the analog filters with different parameter settings and chip configurations.
The project was funded by the SSF INTELECT program.
